preliminary PLL103-07 2 dimm ddr fanout buffer 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 01/03/01 page 1 features generates 12-output buffers from one input. supports via pro266 ddr chipset. supports up to 2 ddr dimms. supports up to 400mhz ddr, sdrams. one additional output for feedback. 6 differential clock distribution. less than 5ns delay. skew between any outputs is less than 100 ps. 2.5v supply range. available in 28-pin ssop. block diagram pin configuration note: #: active low descriptions the PLL103-07 is designed as a 2.5v buffer to distribute high-speed clocks in pc applications. the device has 12 outputs. these outputs can be configured to support 2 ddr dimms. the PLL103-07 can be used in conjunction with the pll202-04 or similar clock synthesizer for the via pro 266 chipset. PLL103-07 28 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 ddrc2 vdd2.5 gnd fbout 13 14 vdd2.5 ddrt0 ddrc0 gnd ddrt1 ddrc1 vdd2.5 buf_in gnd ddrt2 27 22 21 20 19 18 17 16 15 sclk gnd ddrt5 gnd sdata ddrc5 vdd2.5 ddrt4 ddrc4 vdd2.5 gnd ddrt3 ddrc3 vdd2.5 buf_in sdata sclk i2c control ddr0t ddr0c ddr1t ddr1c ddr2t ddr2c ddr3t ddr3c ddr4t ddr4c ddr5t ddr5c fbout
preliminary PLL103-07 2 dimm ddr fanout buffer 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 01/03/01 page 2 pin descriptions name number type description fbout 1 o feedback clock for chipset. buf_in 10 i reference input from chipset. ddrt[0:5] 3,7,12,19, 23,27 o ?true? clocks of differential pair outputs. ddrc[0:5] 4,8,13,18, 22,26 o ?complementary? clocks of differential pair outputs. vdd2.5 5,9,14, 17,21,25 p 2.5v power supply. gnd 6,11,20,24 p ground.
preliminary PLL103-07 2 dimm ddr fanout buffer 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 01/03/01 page 3 i2c bus configuration setting address assignment a6 a5 a4 a3 a2 a1 a0 r/w 1 1 0 1 0 0 1 _ slave receiver/transmitter provides both slave write and readback functionality data transfer rate standard mode at 100kbits/s data protocol this serial protocol is designed to allow both blocks write and read from the controller. the bytes must be accessed in sequential order from lowest to highest byte. each byte transferred must be followed by 1 acknowledge bit. a byte transferred without acknowledged bit will terminate the transfer. the write or read block both begins with the master sending a slave address and a write condition (0xd2) or a read condition (0xd3). following the acknowledge of this address byte, in write mode: the command byte and byte count byte must be sent by the master but ignored by the slave, in read mode: the byte count byte will be read by the master then all other data byte . byte count byte default at power-up is = (0x09). i2c control registers 1. byte 6: outputs register (1=enable, 0=disable) bit pin# default description bit 7 - 1 reserved bit 6 - 0 reserved bit 5 - 0 reserved bit 4 - 0 reserved bit 3 - 1 reserved bit 2 27, 26 1 ddrt5, ddrc5 bit 1 23, 22 1 ddrt4, ddrc4 bit 0 19, 18 1 ddrt3, ddrc3
preliminary PLL103-07 2 dimm ddr fanout buffer 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 01/03/01 page 4 2. byte 7: outputs register (1=enable, 0=disable) bit pin# default description bit 7 - 1 reserved bit 6 - 1 reserved bit 5 - 1 reserved bit 4 12, 13 1 ddrt2, ddrc2 bit 3 - 1 reserved bit 2 7, 8 1 ddrt1, ddrc1 bit 1 - 1 reserved bit 0 3, 4 1 ddrt0, ddrc0
preliminary PLL103-07 2 dimm ddr fanout buffer 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 01/03/01 page 5 electrical specifications 1. absolute maximum ratings parameters symbol min. max. units supply voltage v dd v ss - 0.5 7.0 v input voltage, dc v i v ss - 0.5 v dd + 0.5 v output voltage, dc v o v ss - 0.5 v dd + 0.5 v storage temperature t s -65 150 c ambient operating temperature t a 0 70 c esd voltage 2 kv exposure of the device under conditions beyond the limits specified by maximum ratings for extended periods may cause permanent damage to the device and affect product reliability. these conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. 2. operating conditions parameters symbol min. max. units supply voltage v dd2.5 2.375 2.625 v input capacitance c in 5 pf output capacitance c out 6 pf 3. electrical specifications parameters symbol conditions min. typ. max. units input high voltage v ih all inputs except i2c 2.0 v dd +0.3 v input low voltage v il all inputs except i2c v ss -0.3 0.8 v input high current i ih v in = v dd tbm ua input low current i il v in = 0 tbm ua output high voltage v oh iol = -12ma, vdd = 2.375v 1.7 v output low voltage v ol iol = 12ma, vdd = 2.375v 0.6 v output high current i oh vdd = 2.375v, vout=1v -18 -32 ma output low current i ol vdd = 2.375v, vout=1.2v 26 35 ma note: tbm: to be measured
preliminary PLL103-07 2 dimm ddr fanout buffer 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 01/03/01 page 6 3. electrical specifications (continued) parameters symbol conditions min. typ. max. units supply current (ddr-only mode) i dd unloaded outputs, 133mhz tbm ma supply current (sdram mode) i dd unloaded outputs, 133mhz tbm ma supply current i dds pd = 0 tbm ma output crossing voltage v oc (vdd/2) -0.1 vdd/2 (vdd/2)+ 0.1 v output voltage swing v out 0.7 vdd-0.4 v duty cycle d t measured @ 1.5v 45 50 55 % max. operating frequency 66 170 mhz rising edge rate t or measured @ 0.4v ~ 2.4v 1.0 1.5 2.0 v/ns falling edge rate t of measured @ 2.4v ~ 0.4v 1.0 1.5 2.0 v/ns ddr rising edge rate t or measured between 20% to 80% of output 0.25 0.6 1.0 v/ns ddr falling edge rate t of measured between 20% to 80% of output 0.25 0.6 1.0 v/ns clock skew(pin to pin) t skew all outputs equally loaded 100 ps stabilization time t st 0.1 ms note: tbm: to be measured
preliminary PLL103-07 2 dimm ddr fanout buffer 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 01/03/01 page 7 package information ordering information phaselink corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. the information furnished by phaselink is believed to be accurate and reliable. however, phaselink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. life support policy : phaselink?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of phaselink corporation. for part ordering, please contact our sales department: 47745 fremont blvd., fremont, ca 94538, usa tel: (510) 492-0990 fax: (510) 492-0991 part number the order number for this device is a combination of the following: device number, package type and operating temperature range PLL103-07 x c part number temperaturature c=commercial m=military i=industral package type x=ssop 0.002 - 0.008 (0.0508- 0.2032) 0.396 - 0.407 (10.06 - 10.33) (0.127 - 0.203) 45 0 0.005 - 0.008 0.022 - 0.037 (0.55 - 0.95) 0 0 -8 0 0.015 (0.381) 0.066 - 0.070 (1.676 - 1.778) 0.068 - 0.078 (1.727 - 1.981) 0.0256 0.6502 0.301 - 0.311 7.645 - 7.899 0.205- 0.212 5.207 - 5.385 0.010 - 0.015 0.254 - 0.381 28 pin ssop
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